1. Field of the Invention
The present invention relates to a configuration of a semiconductor integrated circuit device and, more particularly, to a circuit configuration operating at a voltage higher than in other circuit portions in a semiconductor integrated circuit device.
2. Description of the Background Art
In a semiconductor integrated circuit device, for example, in a dynamic random access memory (DRAM) as a semiconductor memory device, generally an internal power supply circuit is mounted, for supplying an internal boosted potential by boosting an externally applied power supply voltage.
More specifically, in a word line potential driving circuit of a DRAM, the above described internally boosted potential is used to make gate potential of an access transistor in a memory cell sufficiently high to prevent voltage drop in the access transistor.
When a sense amplifier band is shared by two memory cell blocks adjacent thereto, a gate circuit for selectively coupling a sense amplifier to a bit line pair in either one of the memory cell blocks is generally formed by an N channel MOS transistor. It is necessary that a signal level controlling such a gate circuit is at a level higher than the xe2x80x9cHxe2x80x9d level potential which can be generated in the bit line pair, that is, the internally boosted potential described above, in order to prevent the voltage drop in the gate circuit.
At this time, the high voltage is applied to the transistor constituting the gate circuit and the access transistor of the memory cell which is the transistor on the side of receiving the high voltage, only when these are selected.
By contrast, the transistor included in the internal power supply circuit for generating the internally boosted potential is subjected to such a high voltage for a longer period, and such a transistor operates under the severest condition considering the necessity of securing reliability.
One of the causes decreasing reliability of such a transistor operating with high voltage applied thereto is a deterioration mode caused by xe2x80x9chot carriersxe2x80x9d generated in a high electric field region near the drain of the transistor.
More specifically, when a transistor is miniaturized while keeping constant the power supply voltage, electric field strength increases near the drain. Therefore, electrons flowing from the source to the drain through the channel obtains high energy from the high electric field near the drain junction, and turn to a so called xe2x80x9chot electrons.xe2x80x9d The hot electrons collide and are ionized near a drain end, generating electrons.holes. Though the electrons flow into the drain, part of the electrons are introduced and captured as a gate current in a gate oxide film and causes increase in threshold voltage or decrease in conductance as time passes.
Degradation of transistor characteristics caused by xe2x80x9chot carriers resulting from impact ionizationxe2x80x9d is said to be more likely in an N channel MOS transistor than a P channel MOS transistor. The reason for this may be the fact that electrons have higher ratio of impact ionization than holes, and that impurity profile of the drain is more steep, and hence electric field near the drain is high.
Accordingly, in a circuit for driving a high voltage such as described above, conventionally, a transistor having an electric field relaxing drain structure, for example, in order to maintain reliability of the N channel MOS transistor, a transistor having an electric field relaxing drain structure, for example, an N channel MOS transistor having an LDD (Lightly Doped Drain) structure has been sometimes used. Alternatively, a circuit configuration has been adopted in which an N channel MOS transistor having a prescribed gate potential applied thereto is interposed between a boosting node and a discharging N channel MOS transistor, so as to relax drain.source voltage.
Recently, in an LSI for image processing, for example, sometimes such a device is manufactured in that a DRAM and a logic circuit are mounted mixed on one chip.
In such a case, generally an MOS insulating film is made thin, for example, insulating film of an MOSFET is made thin (for example, insulating film thickness Tox=2 to 3 nm), in order to improve transistor performance of the logic circuit. Here, the MOS insulating film of the MOSFET in an area where the DRAM is formed is set thicker than in the logic circuit, and the insulating film thickness is Tox=6 to 7.5 nm, for example. Such a structure is referred to as a xe2x80x9cDual-Toxxe2x80x9d method, as MOS insulating films of two different thicknesses are used in one LSI.
Here, up to the generation of the DRAM and the logic circuit having the minimum design dimension of 0.20 micron, an n+-polysilicon gate doped with n type impurity to a high concentration has been used as a gate electrode material both in P channel and N channel MOS transistors. Such a structure of the gate electrode material is referred to as xe2x80x9csingle gate methodxe2x80x9d.
In the single gate method, the N channel MOS transistor is a so called surface channel type MOS transistor, while the P channel MOS transistor is a buried channel type MOS transistor.
More specifically, in the single gate method, generally, an n type polycrystalline silicon (polysilicon) doped with a large amount of phosphorus (P) is used as the gate electrode material. Even in a polycide gate structure consisting of a stacked structure of a high melting point metal silicide and polycrystalline silicon, what is indirect contact with a gate oxide film is n type polysilicon.
When such gate electrode materials are used as the gate electrode of the N channel MOS transistor, the threshold voltage becomes lower, as there is a large difference in work function between a p type substrate and an n type polysilicon. Therefore, generally, in an N channel MOS transistor, impurities of the same conductivity as the substrate are ion-implanted to the channel region, so as to increase the threshold voltage.
When the n type polysilicon is used as the gate electrode of a P channel MOS transistor, the difference of work function between the n type substrate and the n type polysilicon is small, and therefore the threshold voltage increases in a negative direction. Therefore, when the absolute value of the threshold voltage is to be set at approximately the same value as that of the N channel MOS transistor, it becomes necessary that an impurity of an opposite conductivity to the substrate is ion-implanted to the channel region, so as to make smaller the absolute value of the threshold voltage.
As a result, in the P channel MOS transistor having the n type polysilicon as the gate electrode, a very shallow p-n junction is formed in the channel region, resulting in a buried channel type device. By contrast, the N channel MOS transistor having the n type polysilicon gate becomes a surface channel type device.
In the single gate method, the n type polysilicon is used as the gate electrode both in the N channel and P channel MOS transistors, and the threshold voltages of the N channel and P channel MOS transistors are adjusted to be approximately the same, by ion-implantation of boron to the channel region.
When such a structure is adopted, the position where the potential is the minimum is not at the Sixe2x80x94SiO2 interface but in the substrate (well) in the P channel MOS transistor, and therefore, a buried channel is formed.
By contrast, from the generation where the circuit design rule attains 0.18 micron or smaller, a so called xe2x80x9cdual gate methodxe2x80x9d comes to be adopted, in which the gate of the P channel MOS transistor is formed by p+-polysilicon gate and the gate of N channel MOS transistor is formed by n+-polysilicon.
In this case, both P and N channel MOS transistors are the surface channel type MOS transistors.
The reason why such an approach is taken is that the buried channel type device such as the conventional P channel MOS transistor is, though advantageous in that mobility increases as the carriers in the buried channel are less susceptible to the influence of surface scattering particular to the interface, disadvantageous in that short channel effect is likely. Therefore, as the gate dimension reduces, there arises the problems of decreased threshold voltage, degradation in subthreshold characteristic and decrease of punch through breakdown voltage. Possible causes of these problems include that the influence of the gate voltage becomes smaller as the channel position becomes further from the Sixe2x80x94SiO2 interface, and that near the Sixe2x80x94SiO2 interface, the structure along the direction of the channel is p+-p-p+ and there is not the p-n junction, so that the influence of the drain voltage on the channel is increased. Accordingly, it becomes necessary to have the P channel MOS transistor of surface channel type.
In this situation, that is, when a memory circuit such as the DRAM and a logic circuit are formed on one chip and the Dual-Tox method and the dual gate method are employed for the CMOS circuits constituting these circuits, the conventional transistor structure as described above may be insufficient to ensure reliability of the transistor.
An example of a transistor to which the above described high electric field is applied in a DRAM will be described in greater detail.
FIG. 38 is a schematic block diagram illustrating, where a sense amplifier SA has a so called shared amplifier configuration shared by two bit line pairs BL11, /BL11 and BL21, /BL21 in a DRAM, for example, the configurations of a gate circuit for opening/closing the connection between the bit line pairs and the sense amplifier SA and driving circuits DRBI1 and DRBI2 generating a signal BLI for controlling the gate potential of the transistor constituting the gate circuit.
Referring to FIG. 38, sense amplifier SA is connected to bit line pair BL11, /BL11 through gate transistors TG11 and TG12, respectively. Sense amplifier SA is connected to bit line pair BL21, /BL21 through gate transistors TG21 and TG22, respectively.
Gate potentials of transistors TG11 and TG12 are controlled by the signal BLI (i, 0) output from driving circuit DRBI1.
Gate potentials of transistors TG21 and TG22 are controlled by the signal BLI (i, 1) output from driving circuit DRBI2.
Driving circuit DRBI1 includes an inverter INV11 receiving a block selecting signal BSi, P channel MOS transistors TP11 and TN11 connected in series between a boosted potential Vpp and the ground potential GND, and P channel MOS transistors TP12 and TN12 connected in series between the boosted potential Vpp and the ground potential GND.
Transistor TP12 has its gate connected to a connection node of transistors TP11 and TN11, while transistor TP11 has its gate connected to a connection node of transistors TP12 and TN12.
Transistor TN11 receives at its gate a signal BSi, and transistor TN12 receives at its gate an output of inverter INV11.
Driving circuit DRBI1 further includes a P channel MOS transistor TP13 and an N channel MOS transistor TN13 connected in series between the boosted potential Vpp and the ground potential GND.
Transistor TP13 has its gate connected to a connection node of transistors TP12 and TN12, and the potential level at the connection node of transistors TP13 and TN13 is provided as the signal BLI (i, 0).
Driving circuit DRBI2 basically has the same configuration as driving circuit DRBI1. Now, when a logic and a DRAM are mounted together on one chip, the gate length of MOSFET providing the logic circuit is formed with the minimum design dimension, for example, while a transistor having the gate length longer than the minimum design dimension is used as a transistor to which a particularly high voltage is applied, in the DRAM portion 100, such as the transistor TP13.
FIG. 39 is a timing chart illustrating the operation of the circuit shown in FIG. 38.
Referring to FIG. 39, assume that the ith block is selected and the block selecting signal BSi is at an active state (xe2x80x9cLxe2x80x9d level) at time point t0. At time T1, in response to the signal BSI attaining to an inactive state (xe2x80x9cHxe2x80x9d level), transistors TN11 and TN13 in the driving circuit DRBI1 are rendered conductive.
In response, the output of inverter INV1 attains to the xe2x80x9cLxe2x80x9d level, and transistor TN12 is turned off. Therefore, transistor TP12 is rendered conductive, and the gate potential of transistor TP13 increases to the boosted potential Vpp. Thus, transistor TP13 attains to the off state, and the signal BLI (i, 0) attains to the ground potential GND.
At time T2, when the signal BSi attains to the active state (xe2x80x9cLxe2x80x9d level), transistors TN11 and TN13 in driving circuit DRBI1 are set to the off state in response. As the output level of inverter INV11 attains to the xe2x80x9cHxe2x80x9d level, transistor TN12 is rendered conductive. In response, transistor TP11 is rendered conductive, and the gate potential of transistor TP12 attains to the boosted potential Vpp. Thus, transistor TP12 is turned off. In response, gate potential of transistor TP13 attains to the ground potential GND, and therefore, transistor TP13 is rendered conductive and the signal BLI (i, 0) attains to the boosted potential Vpp.
The output level of driving circuit DRBI2 which is not in the selected state, is kept at the xe2x80x9cLxe2x80x9d level.
In such a configuration, P channel MOS transistors TP13 and the like make transition between a state where a potential corresponding to the potential difference between the ground potential GND and the boosted potential Vpp is applied between the source and drain (off state) and a state where the potential difference between the source and the drain is almost eliminated (conductive state).
Here, the transistor TP13 in driving circuit DRBI1 is required to drive, at one time, a plurality of gate transistors (in FIG. 38, only two gate transistors are shown as representatives) existing in the memory cell block, and therefore, it must have a relatively large driving force. Therefore, the time period from the state where the transistor TP13 is in the off state with the ground potential GND and the boosted potential Vpp applied between the source and the drain thereof until the potential difference between the source and the drain of transistor TP13 becomes small is longer than in transistors TP11 and TP12. Therefore, transistors TP13 and the like are kept in such a state in that channel current flows while a larger source.drain voltage Vds is applied.
In the LSI having the DRAM and the logic circuit mounted together, when the CMOS transistor has the dual gate structure and the Dual-Tox method is employed, there is a possibility that sufficient reliability of the P channel MOS transistor such as the transistor TP13 that has been considered less susceptible to degradation in reliability caused by hot carriers, cannot be ensured if such a voltage stress is applied.
An object of the present invention is to provide a semiconductor integrated circuit device capable of ensuring, in a circuit that must drive a relatively high voltage, reliability of a transistor pulling up the voltage.
Briefly stated, the present invention provides a semiconductor integrated circuit device including a logic circuit portion, a voltage down converting circuit, a boosting circuit and a memory portion.
The logic circuit portion operates at the ground potential and a first power supply potential.
The voltage down converting circuit generates, from an external power supply potential, a second power supply potential by down-converting the external power supply potential. The boosting circuit generates a boosted potential, from the external power supply potential, by boosting the external power supply potential.
The memory portion operates at least at the ground potential and the internal power supply potential and the boosted potential, and transmits/receives data to and from the logic circuit portion.
The memory portion includes a plurality of memory cells and a driving circuit. The plurality of memory cells are arranged in a matrix of rows and columns. The plurality of memory cells are each capable of storing any of at least two levels corresponding to the ground potential and the second internal power supply potential.
The driving circuit operates upon reception of the boosted potential and, at least in a data reading operation from the memory cell, generates an internal control signal having a level corresponding to the boosted potential, for controlling the reading operation.
The driving circuit has an output node for outputting an internal control signal, and a surface channel type N channel MOS transistor provided between the output node and the boosted potential, for pulling up the potential level of the output node.
According to another aspect, the present invention provides a semiconductor integrated circuit device including a logic circuit portion, a voltage down converting circuit, a boosting circuit and a memory portion.
The logic circuit portion operates at the ground potential and the first power supply potential.
The voltage down converting circuit generates a second power supply potential from an external power supply potential, by down-converting the external power supply potential. The boosted circuit generates a boosted potential from the external power supply potential, by boosting the external power supply potential.
The memory portion operates at least at the ground potential and the second internal power supply potential and the boosted potential, and transmits/receives data to and from the logic circuit portion.
The memory portion includes a plurality of memory cells and a driving circuit.
The plurality of memory cells are arranged in a matrix of rows and columns. The plurality of memory cells are each capable of storing any of at least two levels corresponding to the ground potential and the second internal power supply potential.
The driving circuit operates receiving the boosted potential, and generates, at least in the data reading operation from the memory cell, an internal control signal having a level corresponding to the boosted potential, for controlling the reading operation.
The driving circuit has an output node for outputting the internal control signal, and a buried channel type P channel MOS transistor for pulling up the potential level of the output node.
According to a still further aspect, the present invention provides a semiconductor integrated circuit device including a logic circuit portion, a voltage down converting circuit, a boosting circuit and a memory portion.
The logic circuit portion operates at the ground potential and a first power supply potential.
The voltage down converting circuit generates a second power supply potential from an external power supply potential, by down-converting the external power supply potential. The boosting circuit generates a boosting potential from the external power supply potential, by boosting the external power supply potential.
The memory portion operates at least at the ground potential and the second internal power supply potential and the boosted potential, and transmits/receives data to and from the logic circuit portion.
The memory portion includes a plurality of memory cells and a driving circuit.
The plurality of memory cells are arranged in a matrix of rows and columns. The plurality of memory cells are each capable of storing any of at least two levels corresponding to the ground potential and the second internal power supply potential.
The driving circuit operates upon reception of the boosted potential, and at least in the data reading operation from the memory cell, generates an internal control signal having a level corresponding to the boosted potential, for controlling the reading operation.
The driving circuit has an output node for outputting the internal control signal, and an LDD type P channel MOS transistor provided between the output node and the boosted potential, for pulling up the potential level of the output node.
According to a still further aspect, the present invention provides a semiconductor integrated circuit device including a logic circuit portion, a voltage down converting circuit, a boosting circuit and a memory portion.
The logic circuit portion operates at the ground potential and a first power supply potential.
The voltage down converting circuit generates a second power supply potential from the external power supply potential, by down-converting the external power supply potential. The boosting circuit generates a boosted potential from the external power supply potential, by boosting the external power supply potential.
The memory portion operates at least at the ground potential and the second internal power supply potential and the boosted potential, and transmits/receives data to and from the logic circuit portion.
The memory portion includes a plurality of memory cells, a driving circuit, a sense amplifier band, a word line driving circuit band, a signal line, a plurality of P channel pull up transistors, and a gate circuit.
The plurality of memory cells are each capable of storing any of at least two levels corresponding to the ground potential and the second internal power supply potential, respectively, and arranged in a matrix of rows and columns. The plurality of memory cells are arranged divided into a plurality of memory cell blocks along the column direction.
The driving circuit operates upon reception of the boosted potential, and generates, at least in the data reading operation from the memory cell, an internal control signal having a level corresponding to the boosted potential, for controlling the reading operation.
The sense amplifier band is provided commonly corresponding to every adjacent pair of memory cell blocks among the plurality of memory cell blocks, and arranged along the row direction for amplifying data read out from the memory cells within the selected memory cell block. The word line driving circuit band is provided along the column direction for every prescribed number of memory cell columns.
The signal line transmits the internal control signal. The plurality of P channel pull up transistors are provided at every intersecting area between the word line driving circuit band and the sense amplifier band, and drive the first signal line level to the boosted potential, in response to activation of the internal control signal.
The gate circuit selectively couples the sense amplifier band with a corresponding memory cell block. The gate circuit includes a plurality of N channel MOS transistors controlled by the potential level of the signal line, for opening/closing coupling between the memory cell block and the sense amplifier portion.
Therefore, a main advantage of the present invention is that at least in the period when a high voltage is applied between the source.drain of the pull up transistor, in driving the internal control signal of the boosted potential level, the potential is pulled up by the N channel MOS transistor. Therefore, degradation of reliability caused by xe2x80x9cchannel hot carriersxe2x80x9d can be suppressed.
Another advantage of the present invention is that, in driving the internal control signal of the boosted potential level, the potential is pulled up by a P channel MOS transistor having such a structure that has immunity to xe2x80x9cchannel hot carriersxe2x80x9d, and therefore degradation of reliability caused by xe2x80x9cchannel hot carriersxe2x80x9d can be suppressed.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.